Step 1: Interconnect dc Current
The user specified input and all device terminal dc currents for a design block in a parasitic extraction file in .spef format.
Ember™ determined the interconnect resistor currents and temperatures and compared the temperatures to the predictions of the foundry's rms density rules.
Ember™ generated the visualisation of temperature on the entire design shown on the Home page. A detail showing a bidirectional interface is given below.
(On the left side of the figure) Six input terminals were given approx. 2 mA (orange) and three were given 0 mA (deep blue). Ember solved for dc current on the interconnect network. Each straight section of interconnect in the figure is a single resistor or via element in the spef.
Step 2: Interconnect Temperature Rise
Trule ≈ 30º C or 0º C (predicted by the foundry's rms current density rules) did not in fact predict any of the temperature rises on these interconnect resistors.
Tmax on each resistor (up to 55.6º C!) was determined by Ember™ according to the closed-form expression max(T(x)) on that resistor. (Note that the current density for the whole length of the leftmost interconnect is uniform, but the temperature rise varies from Tmax=46.5º C to ≈0º C at the via at its right end.)
Ember™ accounts for coupling, finite length, and network effects as effectively as 3D finite difference or finite element calculations requiring orders of magnitude more computational resources.
(Note: large currents specified on poly gates led to very high Tpoly in this example.)
Many resistor temperatures deviate significantly from the foundry rules' implied rms current density temperature rise.
Ember™ reveals hidden reliability problems the current density rules can't see.
Ember™ gives designers the thermal information they need to improve interconnect performance and reliability. Trajectory Design Automation can assist in automating the interpretation of these results.
Resistor Temperature Rise for the Entire Design